Today's high performance data processors execute a complex set of instructions, wherein each instruction is comprised of a sequence of simple machine operations. Typically, these data processors have instructions of varying length (number of machine operations), and execution time (number of clock cycles per instruction). of clock cycles per instruction). These variable length instructions are necessary to facilitate memory accesses by numerous instrucions operating in a variety of addressing modes.
In the conventional data processor each instruction is executed to completion before the next instruction is commenced. In order to improve the efficiency of machine operations, while increasing overall performance, pipelined data processors were implemented in conventional data processor designs. These pipelined data processors are capable of executing several instructions concurrently, thus dramatically improving the overall performance of the data processor. Often, implementation of a pipeline architecture is difficult, due to the variable length of the complex instructions executed by the conventional data processor. The multiple memory accesses associated with some instructions must be detected by the data processor to insure they work properly with I/O peripheral devices. In case where memory mapped I/O references to peripherals destructively change the state of the peripheral device, data read from an I/O port may flush the read buffer, and data written to an I/O port can change the data read from a different port on the same device. Consequently, the sequence of reads and writes must be controlled for the peripheral to function properly.
In some peripherals, the read address and the write address are not identical, therefore, some hardware or software must inform the data processor when a requested access needs serialization. Memory accesses for data processors with write-back buffers may not necessarily occur in the same sequence as the machine code specifies. The data processor must detect the out of sequence read before write access, and multiple access memory accesses (associated with the more complex instructions) to insure they work properly with I/O peripheral devices. The data processor can order the read and write transfers, thereby preventing multiple prefetched reads from the same location, by marking a transfer as "serialized".
In the prior art, are data processors in which the serialization occurs on the processor bus. Typically, in these data processors, the peripheral device responds to its address, once seen on the bus, with a message informing the data processor that the requested access is for a peripheral device, and requesting synchronization of the access. In these data processors the peripheral may not accept the access until the synchronization has occurred. Accordingly, the data processor must suspend the requested access, pending resolution of all write requests and exception conditions. The implementation of this approach requires the utilization of at least one pin encoding on the data processor to accommodate the peripheral handshake signal. Furthermore, additional logic is required to perform the serialization. Some data processors designate a fixed virtual or physical address range as serialized, however, this approach imposes additional limitations on the design of future data processors.